Fanuc 910/911 SRAM Parity Alarm Recovery and Troubleshooting

Introduction

A flashing "BAT" warning on the CNC operator panel is a critical indicator that the 3 V backup battery voltage has dropped below the safe threshold of 2.6 V. If the shop floor leaves this machine powered off and unused for an extended period—such as over a year—with a depleted battery, the entire SRAM data gets destroyed. Upon the next power-up, the operator is met with a devastating RAM parity alarm, bringing the spindle to a hard halt. The immediate consequence of the Fanuc 910 and 911 SRAM Parity Alarms is a complete lockout of all machine functions. Resolving this issue requires a total memory wipe and subsequent recovery. If maintenance personnel fail to correctly restore backed-up system parameters—specifically the software limits defining the chuck and tailstock barrier—the CNC axes can easily overrun their safe travel zones during the next cycle, resulting in a catastrophic physical collision or producing expensive scrap parts. To prevent complete loss of system configuration, setting up a Fanuc automatic data backup cycle is highly recommended for high-production environments.

Technical Summary

System Category	Specification Details
Command Code	Memory All Clear (RESET + DELETE at power-on), SRAM DATA UTILITY (BOOT Menu)
Modal Group	System Recovery / Hardware Diagnostics
Brands	Fanuc
Critical Parameters	0004#3 (NEPRM), 0010#4 (PRG9), 0389#2 (PRG8)
Main Constraint	Recovery demands a complete memory wipe, requiring standard settings, programs, and parameters to be manually or batch re-imported from external backup media.

Quick Read

• A flashing "BAT" warning on the Fanuc control screen indicates the 3 V backup battery is below 2.6 V and needs immediate hot replacement while the CNC remains powered on.
• Extended machine shutdown exceeding one year with a dead backup battery inevitably corrupts the volatile SRAM, triggering Alarm 910 or 911.
• Initializing recovery requires a physical Memory All Clear, executed by holding the RESET and DELETE keys simultaneously during the power-up sequence.
• On Fanuc Series 20i controllers, clearing the SRAM requires a distinct hardware key combination: holding the 7 and 9 keys during boot.
• Restoring custom parameters, especially chuck and tailstock barriers, is mandatory to prevent machine axes from overtraveling and causing hard structural collisions.
• Running parameter edits via the ladder when 0004#3 (NEPRM) is set to 1, followed by another modification with NEPRM set to 0, generates a permanent EEPROM parity mismatch.

Basic Concepts

Fanuc SRAM parity management operates on a precise bitwise and byte-level hardware structure to guarantee continuous data integrity. When data is written to the volatile RAM, a discrete check bit, designated as the parity bit (#P), is appended to the standard 8-bit data byte (#0 through #7). This parity bit is dynamically set to 0 or 1 to force the total count of "1" bits in the byte to be consistently even or odd. Upon reading the memory, the register architecture checks this state; any deviation indicates data corruption and triggers a hardware-level lockout to preemptively stop the machine before the spindle can engage.

Modern Fanuc controllers complement this basic verification by engineering their SRAM arrays with an advanced Error Correcting Code (ECC) algorithm. Instead of relying solely on a simple binary parity check, the system utilizes 8 bits of correction data for every 16-bit word. This allows the CNC to dynamically intercept and correct single-bit memory faults on the fly without halting active production. The control only generates a hard machine interruption, such as Alarm 935, when a multi-bit failure occurs that cannot be corrected automatically by the ECC engine.

To manage this volatile memory environment safely, the CNC features a proprietary BOOT SYSTEM that runs independently of the main CNC software. This isolated layer hosts a dedicated SRAM DATA UTILITY utility screen. This structural independence enables maintenance engineers to cleanly backup or restore the entire SRAM architecture using a PCMCIA or CF card even when a hard parity fault completely freezes the primary operator interface. The precise process of exporting and restoring these memory cards is detailed in the guide on Fanuc SRAM backup and restore, which details manual steps.

Command Structure

System software protection and configuration require precise control over how parameters are stored in the SRAM and EEPROM. Operators must manage specific bit parameters to control edit permissions for critical program ranges and configure how data is committed to non-volatile storage. When editing or storing system macros, setting these registers correctly ensures that the program directories do not get inadvertently modified or corrupted during routine operation.

Special attention is required when interacting with parameter 0004#3. Setting this bit prevents the control from continuously executing writes to the physically limited EEPROM, targeting the faster RAM instead. However, modifying values via the ladder logic when this bit is active, and then subsequently making edits when it is disabled, creates a severe parity mismatch between the volatile and non-volatile layers. This discrepancy forces the system to overwrite custom data on the next reboot.

The physical operations to clear and restore SRAM are executed at the control panel interface during the system boot sequence:

• Standard Memory All Clear: Hold RESET + DELETE keys during power-on.
• Series 20i Memory All Clear: Hold 7 + 9 keys during power-on.
• Programmable Parameter Modification: G10 L50

Parameter	Bit Name	Setting Values	Description and Functional Effect
0004#3	NEPRM	0 or 1	Enables parameter modification in RAM only (1) to prevent excessive wear on the EEPROM, or standard write (0).
0010#4	PRG9	0 or 1	Protects critical system programs in the 9000-9999 range by inhibiting edits (1) or permitting modifications (0).
0389#2	PRG8	0 or 1	Protects custom macro programs in the 8000-8999 range by inhibiting edits (1) or permitting modifications (0).

Brand Applications

Fanuc

On Fanuc CNC systems, SRAM is the core storage area for parameters, pitch error compensation, tool offsets, and macro programs. It relies on a continuous 3 V battery backup to maintain data during power-off states. If a battery voltage drop goes unnoticed, or if the hardware suffers a severe physical shock during transit, parity errors immediately isolate the control and lock out all operations. The recovery procedure requires an intentional Memory All Clear, which completely wipes the SRAM partition. Following the wipe, operators must boot into the proprietary BOOT SYSTEM and navigate to the SRAM DATA UTILITY to restore the system image from a previous backup card. Neglecting to complete a full restore, particularly safety-critical data like axis limit boundaries and tailstock barriers, will lead to mechanical collisions.

Version and Series Comparison

Fanuc Controller Series	Memory Clear Command Keys	Diagnostic & Monitoring Path	Hardware SRAM Mounting Method
Series 15	RESET + DELETE keys at power-on	Monitored via diagnostic address DGN 3016	SRAM module mounted on specialized slots within the primary controller board
Series 16i / 18i / 21i	RESET + DELETE keys at power-on	SRAM utility interface in BOOT SYSTEM menu	Mounted directly on the main CPU board with slot variations between board versions
Series 20i	7 + 9 keys simultaneously at power-on	SRAM utility interface in BOOT SYSTEM menu	Integrated directly on the compact main CPU board architecture

Technical Analysis

The analytical divergence between Fanuc series lies in their physical clearing sequences and diagnostic monitoring interfaces. While standard controllers like the Series 16i, 18i, and 21i rely on the dual-key RESET and DELETE combination during startup to reset SRAM, the Series 20i requires a specialized hardware-level bypass holding the 7 and 9 keys. This prevents accidental execution of a full wipe on compact lines. From a diagnostics perspective, diagnostic mapping presents a distinct shift. The legacy Series 15 utilizes diagnostic register DGN 3016 to actively track memory bus states, whereas modern Series 16i and 18i controls shift this oversight to dynamic BIOS-level screens, managing memory slot mapping directly across varying main CPU motherboard revisions.

Program Examples

%
O1001 (SRAM PARAMETER AND MACRO TEST) ;
G90 G17 G40 ;
G10 L50 ; (Enable programmable parameter write to alter SRAM registers)
N9000 P0010 R00000000 ; (Modify Parameter 0010 bit 4 to 0 to enable program edits)
G11 ; (End of programmable parameter input)
M98 P9000 ; (Call protected subprogram P9000 residing in SRAM memory)
M30 ; (End of program, rewind program pointer to beginning of memory)
%

dry run

• In a dry run execution or offline test environment, this code block demonstrates how to programmably access and alter SRAM parameters before executing a macro call.
• The command G10 L50 opens the parameter entry mode, targeting the volatile SRAM registers directly.
• The parameter line modifies the state of the protection bit (setting the PRG9 bit of Parameter 0010 to 0) to allow modifications to the 9000-range subprograms.
• The G11 command terminates the data entry mode, writing the updated state.
• The command M98 P9000 is then executed, calling subprogram 9000 from the SRAM memory space.
• Finally, M30 terminates the program, resetting the active program pointer back to the beginning of the program memory.

Error Analysis

Brand	Alarm Code	Trigger Condition	Operator Symptom	Root Cause & Resolution
Fanuc	Alarm 910	RAM parity error detected in the low byte (Byte 0) of the tape memory RAM module.	Immediate machine cycle stop, red alarm light illumination, and total system lockout.	Corrupted low-byte registers or a physical failure in the master PCB memory bus. Requires an intentional Memory All Clear (RESET + DELETE at power-on) and a clean restore from backup. If the alarm persists, replacement of the master CPU board is required.
Fanuc	Alarm 911	RAM parity error detected in the high byte (Byte 1) of the SRAM module.	Total operational lockout with diagnostic screen displaying the high-byte parity fault.	Data corruption in the high-byte memory registers or a failed FROM/SRAM module. Resolution requires executing a full memory wipe during boot and re-importing the parameter suite. Module replacement is necessary if physical hardware damage is present.
Fanuc	Alarm 935	Error Correcting Code (ECC) check detects a multi-bit failure in the SRAM part program storage that cannot be corrected automatically.	Spindle stop, axis motion halt, and system shutdown with Alarm 935 displayed. Also, while SRAM parity alarms stop the entire control system, axis-specific issues like the SV0411 servo deviation alarm indicate feedback loop anomalies.	Multiple bits in a 16-bit word have failed concurrently, exceeding the single-bit self-correction limit of the ECC algorithm. This requires clearing the program memory via the boot menu, re-initializing the space, and restoring the files. If the fault recurs, replace the physical SRAM chip.

Application Note

A catastrophic axis overrun leading to a severe physical collision with the vise jaw or chuck is the immediate risk if maintenance personnel fail to restore backed-up chuck and tailstock barrier parameters after a memory clear. During routine backup routines, the CNC boot system aggressively scans the entire SRAM space. This scan can trigger a sudden parity error even in an unallocated or unused memory sector while the machine is apparently running normally. Executing a comprehensive Memory All Clear safely reinitializes these unallocated dead zones, neutralizing the false trip and permitting a clean reload of the master parameter files. Shop technicians must strictly verify these barrier parameters before enabling automatic cycle execution to ensure the tool path remains within safe physical bounds.

Related Command Network

• RESET + DELETE Keys (Memory All Clear): Wipes the entire SRAM partition at startup to eliminate parity alarms and initialize clean memory spaces.
• 7 + 9 Keys (Series 20i Memory Clear): Serves as the specialized dual-key startup bypass required specifically to clear volatile memory on Fanuc Series 20i controls.
• SRAM DATA UTILITY: Operates within the standalone BOOT SYSTEM menu to permit batch-saving and batch-restoring of the entire SRAM configuration via memory card.
• G10 L50 (Programmable Parameter Input): Enables automatic writing of parameters and register values directly into the active SRAM partition from within a part program.
• M98 P9000: Invokes subprograms and custom macros stored in the protected SRAM memory space under parameter lock.

Conclusion

Ensuring continuous machine uptime relies on an active preventative maintenance schedule that combines immediate battery replacements with periodic SRAM image backups. When faced with a hard lockout from Alarm 910 or 911, executing a system-level memory clear and utilizing the isolated BOOT SYSTEM menu to restore the parameter backup is the only viable path to resume safe production.

Frequently Asked Questions

How can you prevent a false SRAM parity alarm in unallocated memory sectors

A false parity alarm occurs when the boot system scans unallocated or unused memory zones that contain random, non-initialized bit states. To prevent this from disrupting production, perform a proactive Memory All Clear by holding the RESET and DELETE keys during a scheduled maintenance shutdown. This physical wipe reinitializes every sector of the SRAM array, making sure that subsequent system-wide scans read clean, verified states throughout the entire partition.

What should you do immediately when the flashing BAT warning appears on the display

A flashing BAT warning indicates that the backup battery voltage has dropped below 2.6 V, leaving you with limited time before data loss occurs during shutdown. You must immediately replace the 3 V lithium battery while the CNC control is powered on. Performing this replacement under power maintains the voltage supply to the SRAM, protecting your custom parameters and programs from being erased while the battery is unplugged.

Why does parameter 0004#3 generate a parity mismatch error after ladder modifications

Setting the NEPRM bit of parameter 0004#3 to 1 redirects parameter modifications to write to the RAM only, protecting the EEPROM from write wear. If you alter parameters via the ladder logic under this setting and then change NEPRM back to 0 before executing subsequent parameter modifications, the control detects a severe mismatch between the RAM and EEPROM states on boot. To resolve this, ensure that all ladder-based parameter writes are fully completed and verified before toggling the NEPRM bit state back to its default value.